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Ordering number : EN4128B
CMOS LSI
LC8900KQ
Digital Audio Interface Receiver
Preliminary Overview
The LC8900KQ is a CMOS LSI circuit chip that can be used to enable the EIAJ CP-1201 formatted data transmission between digital audio equipment. It is used by the receiving end and operates synchronously with input signals. This chip demodulates input signals into normally-formatted signals.
Applicational and Functional Concept
Features
* On-chip PLL circuit: enables the LSI operation to be synchronous to the transmitted EIAJ format input signals. * Four input pins and one output pin: The output pin enables the input data to be sent as they are. * Two data output function modes: 20-bit data LSB first mode and 16-bit data MSB first mode. * Four output clocks: Bit clock, LRCK, 384Fs and 256Fs. All these clocks are synchronized to the data. * Various signal outputs: copy inhibit, emphasis on:off control, user's bit, validity flag and sampling frequency. * LPF time constant select mode: This function can be used in the PLL lock-up state. * Error detect signal output: If an input data error is detected, this LSI circuit chip outputs the error signal. In this case, the previous data will be output by the chip. * Lock-up signal output: This signal is output when the internal PLL (Phase Locked Loop) block of the LSI circuit chip is locked. * The chip has the pin to receive a signal for stopping the PLL operation. * Control and processing mode via microcontroller interface: input pin select, copy information and sampling frequency output. * Each input pin has an internal amplifier circuit. * Si gate, CMOS process technology and single 5V power supply applicational and functional concept.
Package Dimensions
unit:mm
3148-QFP44MA
[LC8900KQ]
SANYO: QIP44MA
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
83096HA (OT)/7062JN No. 4128-1/12
LC8900KQ Pin Assignment
Block Diagram
No. 4128-2/12
LC8900KQ Pin Functions
Pin No. 1 2 3 4 5 6 7 Pin Name DOUT RC1 RC2 SEL1 SEL2 LPF STOP I/O Type O I O I I I I I 8 OUTMODE Functional Description Input data output pin. However, its output is fixed at the low level if the DIN4 input pin is selected. RC oscillation pin RC oscillation pin Input pin select pin Input pin select pin High level = LPF time constant select mode. low level = LPF time constant fixed mode. Fixed to high in most cases. High = level:Forces the VCO operation to stop. Fixed to low in most cases. Output data format select pin. High = 20-bit LSB first data format. Low = 16-bit MSB first data format 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 TEST2 XMODE DVDD AVDD R AGND Vin VCO DGND TEST1 V FS256 FS384 DVDD BCLK DATAOUT LRCK EMPHA LOCK ERROR COPY BSA CD BSB U DO DI CE CL MODE DVDD DIN1 DIN2 DIN3 DIN4 DGND I I I I O O O O O O O O O O O O I O O I I O O O I O I I I Test pin:Connected to the DGND in most cases. Input pin to start the PLL operation immediately after the LSI chip is powered on. Digital power supply Analog power supply VCO oscillation bandwidth adjust pin Analog ground VCO self oscillation frequency setting pin PLL LPF pin Digital Ground Test pin:Connected to the DGND in most cases. Validity flag output pin 256 Fs clock output pin 384 Fs clock output pin Digital Power Supply Bit clock output pin Audio data output pin L/R clock output pin, Lch = high, Rch = low Emphasis control (on/off) output pin:High = emphasis mode. Low = none-emphasis mode. PLL lock state output pin:High = PLL locked state. Low = PLL unlocked state. Input data error detect signal output:High = error detected. Copy information output pin Input data sampling frequency indication:High = 2 kHz. Input data sampling frequency indication:High = 44.1 kHz. Input data sampling frequency indication:High = 48kHz. User's bit output pin Microcontroller interface output pin Microcontroller interface input pin Microcontroller interface chip enable input pin Microcontroller interface clock input pin Microcontroller interface control input:High = microcontroller interface active mode. Low = microcontroller interface inactive mode. Digital power supply Data input pin Data input pin Data input pin Data input pin Digital ground
No. 4128-3/12
LC8900KQ
Specifications
Absolute Maximum Ratings at Ta = 25C
Parameter Maximum supply voltage Input/output voltage Ambient operating temperature Ambient storage temperature Symbol VDD max VI * VO Topr Tstg Ta = 25C Ta = 25C Conditions Ratings -0.3 to +7.0 -0.3 to VDD +0.3 -30 to +75 -55 to +125 Unit V V C C
Allowable Operating Range at Ta = -30C to +75C
Parameter Supply voltage Symbol VDD Conditions min 4.5 typ 5.0 max 5.5 Unit V
DC Characteristics at Ta = -30 to +75C, VDD = 4.5 V to 5.5 V
Parameter Input high level voltage Input low level voltage Input high level voltage Input low level voltage Output high level voltage Output low level voltage Current drain Input amplitude Symbol VIH VIL VIH VIL VOH VOL IDD VIN *1 *1 *2 *2 IOH = -1 A IOL = 1 A *3 *4 0.4 11 Conditions min 2.2 -0.3 0.8 VDD -0.3 VDD - 0.05 VSS + 0.05 12 VDD + 0.3 typ max VDD + 0.3 0.8 VDD + 0.3 0.2 VDD V V mA VP-P Unit V V V
AC Characteristics at Ta = -30 to 75C, VDD = 4.5 to 5.5 V
Parameter Output pulse width Output set-up time Output data hold time Symbol tWBO tDSO tDHO Fs = 48kHz Conditions min 160 80 80 typ max Unit ns ns ns
Note 1: All input pins except DIN1, DIN2, DIN3, DIN4 and XMODE. Note 2: XMODE pin Note 3: VDD=5.0V, Ta = 25 C, input Fs=48 kHz. Note 4: Before DIN1 to DIN4 input capacity is exceeded.
No. 4128-4/12
LC8900KQ AC Characteristics at the Microcontroller Interface Block at Ta = -30 to +75C, VDD = 4.5V to 5.5V
Parameter CL low pulse width CL high pulse width Data set up time Data hold time CL rise time CL fall time CE delay time CL delay time Data delay time CL/data delay time CL delay time CL/CE delay time Symbol TWL TWH TDS TDH Tr Tf TD1 TD2 TD3 TD4 TD5 TD6 Load capacitance = 30 pF Load capacitance = 30 pF 100 1.0 CL, CE, DI CL, CE, DI 1.0 50 25 50 Conditions min 100 100 50 50 30 30 typ max Unit ns ns ns ns ns ns s ns ns ns ns s
AC Characteristics at the Microcontroller Interface Block
No. 4128-5/12
LC8900KQ PLL VCO Functional Circuit Block VCO
* The VCO (Voltage Controlled Oscillator) functional block consists of multiple ring oscillator ad shown above. * The ring oscillator produces the frequencies from 3 MHz to 40 MHz according to the VCO pin voltages 0 V to 3 V. * The VCO self oscillation frequency is determined by the VIN pin voltage.
Phase Detector * The phase detector circuit operates on the rising edge of the incoming signals. It compares the clock generated from the input signal with the VCO clock.
LPF (Low-pass filter)
* The charge pump and the LPF are shown above. The LPF time constant varies depending on the lock judge signal.
No. 4128-6/12
LC8900KQ DATA (1) The relationship between the data input pins and the data select pins are shown in the table below.
SEL1 DIN1 DIN2 DIN3 DIN4 L L H H SEL2 L H L H DOUT DIN1 data output DIN2 data output DIN3 data output low level signal output (fixed level output)
* Each input pin has an internal amplification circuit. Therefore the signal with the amplitude of 400 m VP-P up to VDD+0.3 V can be input to this LSI chip. However, in the case of coaxial cable or optical module input the application will change as the sample application circuit shown later. * Connect to the unused input pin to the GND or VDD. (2) The relationship between the OUTMODE pin and the two output data formats is shown in the table below.
OUTMODE pin H L 20-bit LSB first data output format 16-bit MSB first data output format
* IF an error is detected in an input data, that input data is not output. Instead, the previous data will be output. * The data output is synchronized with falling edge of the bit clock. * IF the PLL is in the Lock state, the 384 Fs or 256 Fs clock that is synchronized with the output data will be output. Note that the duty is of the 256 Fs clock is 'H:L = 2:1'. It is not 'H:L = 1:1'. Sub Codes The sub code output consists of the copy inhibit signal, emphasis mode signal, sampling frequency signal, validity flag signal and user's bit. The table below details these sub code outputs.
COPY inhibit signal COPY pin level = high:Copy not inhibited. COPY pin level = low:Copy inhibited. Emphasis mode signal EMPHA pin level = high:Emphasis mode. EMPHA pin level = low:Non emphasis mode. BSA pin level = high:32 kHz sampling frequency Sampling frequency CD pin level = high:44.1 kHz sampling frequency BSB pin level = high:48 kHz sampling frequency Validity flag signal User's bit This signal is output from the V pin in sub frame unit. This signal is output from the U pin in sub frame unit.
Clock Modes The control clock is specified by the VCO. The VCO has two modes: self oscillation mode and PLL mode as shown below.
* XMODE pin level=low Self oscillation mode * No data input PLL mode * Data input with the XMODE pin level=high * The VCO continues its oscillation according to the VIN pin potential. BCLK, LRCK, and FS256 clocks are not effective. * The VCO continues its oscillation according to the VIN pin potential. FS384, BCLK, LRCK, and FS256 clocks output. * The PLL block and the entire circuit are in the normal operation state.
* When the STOP pin is changed to the high level, the PLL functional circuit block stops its operation and the entire circuit operation is then forced to stop. The entire circuit will start the normal operation again when the STOP pin is changed to the low level. * If the LOCK operation is not activated in a certain fixed time period after the PLL enters the lock-up state: Reinitialize the PLL functional circuit block to active the lock-up mode. This should be done to prevent the PLL lock error.
No. 4128-7/12
LC8900KQ Microcontroller Interface The microcontroller interface function can be used by setting the MODE pin level to high. In this function mode, the pins CE, CL, DI and DO can be used to allow the interface between the LSI chip and a microcontroller. This microcontroller interface allows the microcontroller to control and process the input pin selection output data format, copy information and sampling frequency output. Set the mode CE, CL, and DI pins to the low when the microcontroller interface is not used. Input data format
Output data format
Bits B0 to A3 of the DI signal in the format figures on the preceding page are used to specify an 8-bit address. These 8bits are used to specify the addresses both in the input and output operations.
B0 Data input mode Data output mode 1 0 B1 0 1 B2 1 1 B3 0 0 A0 0 0 A1 1 1 A2 1 1 A3 0 0
(1) Data input mode Bits DI0 to DI4 of the DI signal are used to select the operation modes shown in the tables below.
DI1 = L 16-bit data MSB first output mode DI1 = H 20-bit data LSB first output mode
DI2 L L H H
DI3 L H L H
input pin selection DIN1 DIN2 DIN3 DIN4
DOUT DIN1 data output DIN2 data output DIN3 data output low level signal output (fixed level output)
* When the MODE pin level is set to high, the input pins and output data format are selected by the microcontroller. This means that the selection data input to the SEL1, SEL2 and OUTMODE pins has no significance. Just after the XMODE pin is changed to high from low, DI0 to DI4 are set to low.
No. 4128-8/12
LC8900KQ (2) Data output mode Bits DO0 to DO4 of the DO signal have the following meanings show in the tables below.
DO3 = L Copy inhibited DO3 = H Copy not inhibited
DO1 L L H
DO2 L H H
Sampling frequency selection 44.1 kHz 48 kHz 32 kHz
* 6 ms or longer is required to read data after the ERROR pin is changed to L. Take at least 6 ms between data read out. Any codes when DO1 is high and DO2 is low is invalid in other conditions than this. Timing Chart
No. 4128-9/12
LC8900KQ LOCK and ERROR Pins Descriptions of LOCK and ERROR pins are as follows. LOCK: Preamble detector. When two or more preambles are detected successively, this pin outputs high level signal. When XMODE pin is low or STOP pin is high or no signal input, outputs low level signal.
ERROR: When two or more preambles are not detected successively, or 8 subframes' continuous results of parity check are not accomplished, this pin outputs high level signal to indicate system error. When XMODE pin is low or STOP pin is high or no signal input, outputs high level signal. 1. Output pin conditions when error occurs.
Output pin DATAOUT V U CD, BSA BSB, COPY EMPHA DOUT XMODE is low Keeps the indeterminate condition of high or low. Outputs low level signal. STOP is low Keeps the value just before the STOP goes to high. Outputs low level signal. Parity error Outputs preceding data. No input signal Outputs the indeterminate data. *1 Outputs the indeterminate data. *1 No effect by error.
Outputs low level signal after reset. No effect by error.
No effect by error.
No effect by error.
Note 1: When input pin goes to no input signal, errors can be caused due to the timing of turning into no input signal. Take the same operation as parity error in this case. 2: When error occurring, the outputs pin's change synchronizes the timing of ERROR pin's turning into the high level. When XMODE pin is set to low or STOP pin is to high, ERROR pin goes to high at the same time and the other output pins will change as in the table above.
2. Error signals and read out timing After the ERROR pin goes to low, each data will be able to be accessed after the next clock pulse.
DATAOUT, V, U CD, BSA, BSB, COPY, EMPHA Accessible as soon as ERROR pin goes to low Accessible 6 ms or later after ERROR pin goes to low
XMODE Pin XMODE pin resets the system. This pin must be turned into high after 4.5 V or more power is applied to start the system normally. By setting XMODE pin to low, VCO self oscillation frequency from FS384 pin will reset the internal circuit. Power rise diagram
Each input pin will be accessible after XMODE turns to be on to start the system. Microcontroller interface pins will be accessible after XMODE turns to be on to start the system. Each data output pin will be accessible after XMODE turns to be on and ERROR pin goes to low. COPY, EMPHA, CD, BSA, and BSB cords will be accessible at least 6 ms later after ERROR pin goes to low.
No. 4128-10/12
LC8900KQ Sample Application Circuit
Apply the power to AVDD and two DVDDs simultaneously, or a latch up will occur. The allowable current to BSA, CD, and BSB pins is 8 mA.
No. 4128-11/12
LC8900KQ Recommended External Components
Component type Component code R1 R2 R3 R4 Resistor R5 R6 R7 R8 R9 C1 Capacitor C2 C3 C4 *: Value 330 k* 33 k 10 k 24 k 5.1 k 5.1 k 150 180 k 330 0.1 F 1000 pF 10 F to 100 F 0.01 F
This is a value when coaxial cables are connected to the input pins. Take C1 and replace R1 with a 56 k resistor if optical cables are connected instead of coaxial cables.
Connection to an Optical Module
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of November, 1997. Specifications and information herein are subject to change without notice. No. 4128-12/12

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